Learn about Digital Demultiplexers with interactive circuit diagrams, truth tables, Boolean expressions, selection logic, logic gate implementation, and digital logic examples.
A demultiplexer takes a single data input and routes it to exactly one of several outputs, based on the value of its select lines. With two select inputs S1S0, the 1:4 DEMUX steers the data line D through to one of four outputs Y0–Y3 — Y0 = D·S1'S0', Y1 = D·S1'S0, Y2 = D·S1S0', Y3 = D·S1S0. Each output needs an inverted select (NOT), a select-minterm AND, and a data AND — a three gate delay circuit.
| S1 | S0 | Routed to | Y0 | Y1 | Y2 | Y3 |
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