Learn about Arithmetic Logic Units (ALUs) with interactive block diagrams, arithmetic operations, logical operations, control signals, logic circuit implementation, and digital system examples.
An ALU combines an adder/subtractor and a logic unit behind a shared output mux, selected by an opcode. B is conditioned through a XOR-with-SUB stage so the same adder performs both A+B and A−B (via B's two's-complement), while the logic unit produces AND / OR / XOR / NOT in parallel. The mux then picks which result reaches F, and flags are derived from it — Z = NOR(F), N = F3, C = adder carry-out, V = signed overflow, both only meaningful on arithmetic ops. Critical path is a four gate delay circuit (COND, ALU-CORE, MUX, FLAGS).
| Op | Function | Adder | Logic unit | C valid | V valid |
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